In electronics, a phase-locked loop (PLL) is a closed-loop feedback control system that generates and outputs a signal in relation to the frequency and phase of an input (“reference”) signal. A PLL circuit responds to both the frequency and the phase of the input signal, automatically adjusting the frequency and phase of a controlled oscillator until the frequency and phase match that of the reference signal. This type of mechanism is widely used in radio, telecommunications, computers, and other electronic applications where it is desirable to stabilize a generated signal or to detect signals in the presence of noise. Since an integrated circuit can hold a complete phase-locked loop building block, the technique is widely used in modern electronic devices, with signal frequencies from a fraction of a cycle per second up to several gigahertz (GHz).
Circuit designers often use digital PLL circuits as master clock synthesizers for microprocessors and key components of universal asynchronous receiver transmitters (UARTs). PLLs generally contain a phase detector, low pass filter, and voltage-controlled oscillator (VCO) placed in a negative feedback configuration. There may be a frequency divider in the feedback path or in the reference path, or both, in order to make the output clock of the PLL a rational multiple of the reference frequency. The oscillator generates a periodic output signal. Depending on the application, either the output of the controlled oscillator or the control signal to the oscillator provides the useful output of the PLL system.
PLLs are widely used for synchronization purposes. Circuits commonly send some data streams, especially high-speed serial data streams (such as the raw stream of data from the magnetic head of a disk drive), without an accompanying clock. The receiver generates a clock from an approximate frequency reference, and then phase-aligns to the transitions in the data stream using a PLL. This process is referred to as clock data recovery (CDR). Another use for PLLs is clock multiplication. Most electronic systems include processors of various sorts that operate at hundreds of megahertz. Typically, the clocks supplied to these processors come from clock generator PLLs, which multiply a lower-frequency reference clock (usually 50 or 100 MHz) up to the operating frequency of the processor. The multiplication factor can be quite large in cases where the operating frequency of the processor is multiple gigahertz and the reference clock is just tens or hundreds of megahertz.
While PLLs are very broadly used, unfortunately they are not suitable for some applications because the large number of components in a PLL cause the PLL to consume a significant amount of power. For example, mobile device manufacturers might prefer the functionality of a PLL to perform CDR and clock multiplication for high-speed data transfers. The battery drain inherent in a PLL, however, and the impact on battery life of a mobile device often mean that manufacturers must elect to use other technologies or end up compromising the device performance.